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An Address Generation Interlock happens in a pipeline when a register being used as a base or an index was the destination of the preceding instruction. Normally, the calculation of the address needed by an instruction which accesses memory is done at a separate stage in the pipeline while the previous instruction is executing. AGIs are a Bad Thing because the instructions can't be executed in parallel due to their dependancy on each other.

Example (in x86 asm):
add eax, 4
mov ebx, [eax]

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