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Most microcontrollers on the market today have two basic architectures, each with two variants. One architecture refers to the type of bus design used for the program and data memory: von Neumann vs. Harvard. The other classification describes the type of instruction set and the complexity of the CPU: CISC vs. RISC. Microcontrollers from Motorola, Intel, Zilog and National Semiconductor all have von Neumann architecture and CISC underpinnings.

Harvard architecture has separate program and data memory busses. The program memory bus is variable in width and optimized for a particular device. The data bus width is usually a standard 8 or 16 bits. The special function registers (timer settings, port configuration, etc.) are also mapped onto the data bus because they are essentially variables. This architecture allows the simultaneous access of both program memory and data memory.

Harvard architecture has several benefits, mainly a long word instruction that occupies only one location in program memory. A single word instruction increases the execution speed because the opcode and associated data are all contained in a single word. The single cycle instruction execution is also easily performed in the Harvard architecture because the program and data memory can be accessed at the same time.

A popular maker of Harvard architecture chips is Microchip, who makes the PIC series; by some accounts, they are the #2 microprocessor maker! This is largely due to use in consumer electronics. Scenix is Microchip's AMD: Faster, cheaper, code-compatible, not as diverse.

Actually, most high end cpu's today are a mixture of Harvard and von Neumann architectures.

On the outside, they are von Neumann, with a single bus for data and program memory. Superficially, the memory is byte structured; however, the actual bus is probably word structured, for higher throughput. Some even require or prefer program and data to be word aligned. Misalignment carries the penalty of either decreased performance or a bus error, depending on the architecture.

Internally, the cpu is Harvard architecture. The core of the cpu is buffered from the outside bus by high speed cache memory and a cache controller. For higher performance, the cpu internally has a separate program bus and data bus, each with their own cache. The cache controller for the data cache does bus snooping to update the copy in cache if other devices on the bus change main memory. However, the instruction memory is typically not kept up to date, as this both reduces circuitry in the cpu and increases performance.

As a consequence of this, once in cache, the program memory is essentially read only, which is typical of Harvard architecture. This makes self modifying code tricky, as the program must be modified before the code is ever run, or the cache must be flushed (either by an explicit invalidation or by waiting for the cache line to be replaced with another) before the modifications become effective.

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