Imperfect pairing

On Pentium and above processors, there are situations where two paired instructions will not execute at the same time, or only partially overlap, becoming an imperfect pair. They're still considered a pair because the first instruction executes in the U-Pipe and the second in the V-Pipe. No following instruction can start to execute before both instructions have been finished.

Imperfect pairing occurs in the following cases:

• The second instruction suffers an Address Generation Interlock stall.
• Two instructions access the same DWORD of memory simulataneously.
• Two instructions access memory addresses where bits 2-4 are the same. (cache bank conflict)
• A read/modify/write instruction is paired with a read/modify memory or read/modify/write memory instruction.
• A pairable floating point instruction is followed by FXCH and the next instruction is not a floating point instruction
• Two paired instructions take extra time due to cache misses, misalignment, or branch misprediction.