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The MESI protocol is a method of insuring cache coherence in a multiprocessor machine. With shared memory and more than one processor, it is vital to ensure that data in a processor's cache is an accurate reflection of main memory. The MESI protocol was developed at the University of Illinois and is used by the Pentium family of processors. MESI stands for Modified, Exclusive, Shared, and Invalid which are the four extra bits stored with each cache line in order to track its modification status within the shared memory system. Here is a brief explanation of what the four states mean for data in a cache.
  • Modified - Dirty bit, data needs to be written to memory
  • Exclusive - Only this cache has a copy and it is unmodified
  • Shared - two or more caches contain this data
  • Invalid - Data is invalid

Illustration of the MESI protocol
              Read/Modify from
  .----------.   other cpu     .-----------.
  | INVALID  |<----------------|  SHARED   |
  '----+----+'       +---------'-----------'
       |    |        | Modify        ^
  Read/|    |        |               |Read from
 Modify|    +--------+-----------+   |other cpu
       V             |      Read |   |
  .----------.<------+         .-V---+-----.
  | MODIFIED |<----------------| EXCLUSIVE |
  '----------'      Modify     '-----------'
This illustration is trying to show how the bits are set when certain operations occur. This is a simplification of the full MESI protocol, but the basics are here. For example, if a piece of data is marked SHARED, and its own CPU modifies the data, it will move to the MODIFIED state. If a different CPU modifies shared data, then move to the INVALID state by invalidating all other copies of that cache data. The lines that don't exist keep the status the same, for example if you are in the exclusive state, and read your own data, then you stay in the exclusive state.

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