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The Widlar source was designed by and named for Bob (Robert) Widlar, who worked for National Semiconductor and produced a number of very profitable designs. The Widlar source is an important analog building block. When combined with other blocks such as the differential pair and the current mirror, it can be used in the design of operational amplifiers (op amps), operational transconductance amplifiers, and other such circuits.

A Widlar current source is used in analog integrated circuit design to produce a small driving current without the use of large resistors. This is particularly important because it is difficult to produced large resistors on chip that have good tolerances, meaning that it is very difficult to get predictable, reliable currents using large resistors.

The Widlar source uses two transistors fabricated with their bases connected together, and two small resistors. One of the transistors has its base connected to its collector, forming a diode connected transistor.

The input current is fed into the collector of the diode connected transistor, and a small current results at the collector of the other transistor. A crude ASCII circuit diagram may help:

```+Vcc
----
|
|-------------
|            |
|   |        |
|   |  Ie1   |
\  \|/       |
/            |
/            |   |  Ie2
|            |  \|/
|------      |
C1\     |      /C2
\    |     /
\|  |   |/
Q1 |------| Q2
/|B1  B2|\
/          \
E1/            \E2
|            |
|            \
|            /
|            \ R2
|            /
|            |
|            |
-------------|
|
---
-  GND
```

I've labeled the base, emitter, and collector terminals of Q1 and Q2 because I'm stuck on how to do the diode triangle thing that appear on the emitter terminal in ASCII...

Okay, if we assume that the transistors are operating in their active regions (which is a good assumption as long as the voltage at the collector of Q2 is greater that about 0.7 V for bipolar devices), then the input current Ie1 through R1 is given by:

Ie1 = (Vcc - 0.7) / R1

The voltage at the base and collector of Q1 is assumed to be 0.7 when Q1 is in its active region and when the operating temperature is about 20 degrees Celsius.

Having the input current, we can find the output current iteratively using the Widlar design equation:

I2 = (Vt/R2) ln (I1/I2)

Vt can be assumed to be 26mV at room temperature, and we know I1 from the previous calculation. If we are designing toward a target output current, we would plug that current in and solve for R2. Otherwise, an iterative solution (done by plugging in values for I2 and seeing if the result matches) is required.

The derivation of the Widlar design equation is quite straight forward; it comes from writing a loop equation for the bottom loop in the diagram, using the Ebers-Moll equations to model the transistors (you can't assume a 0.7 V drop across the emitter-base junction in this case). Interested parties can look it up in a textbook on analog IC's, such as Microelectronic Circuits by Sedra & Smith.

### References:

Memory, and my ENEL 465 class notes.

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