shift register

This can be accomplished by interconnecting the individual flip-flops in a register. Any register with a serial input or output must have some shifting ability in order to access all of the data in the register; however, even registers with only parallel input/output can still have shifting ability.

Here is a simple 4-bit serial input, parallel output register:

                 P3           P2           P1           P0
                 |            |            |            |
      +--------+ | +--------+ | +--------+ | +--------+ |
I--+--|S   Q(H)|-+-|S   Q(H)|-+-|S   Q(H)|-+-|S   Q(H)|-+
   |  |        |   |        |   |        |   |        |
  --- |   SR   |   |   SR   |   |   SR   |   |   SR   |
  \_/ |  Flip  |   |  Flip  |   |  Flip  |   |  Flip  |
   o  |  Flop  |   |  Flop  |   |  Flop  |   |  Flop  |
   |  |        |   |        |   |        |   |        |
   +--|R   Q(L)|---|R   Q(L)|---|R   Q(L)|   |R   Q(L)|
clk-+-|>       | +-|>       | +-|>       | +-|>       |
    | +--------+ | +--------+ | +--------+ | +--------+
    +------------+------------+------------+

I is the serial input, P3-P0 is the parallel output. P0 can also be used as a serial output. This devices shifts right; that is, on each clock pulse each bit becomes 1 bit less significant.

This sort of scheme is also necessary for the use of a serial line; if a whole byte is desired to be sent, it much be reconstructed at the receiver, since it can only be sent over the serial line one bit at a time. Obviously, it takes time to reconstruct the data sent over the serial line; here 4 clock cycles are necessary to reconstruct a single nibble sent through I, and the least significant bit must be sent first.

See also sequential arithmetic, arithmetic logic unit, universal shift register, bus, SR Flip-Flop, D Flip-Flop, JK Flip-Flop, direct clear, direct set, multiplexer, decoder, transmitter.