L2 cache (thing)

Back in the days of the original Pentium, and the 486, L1 cache resided on the CPU, and thus had very low latency and high bandwidth. But system DRAM was quite slow. A lot of CPU cycles were wasted when L1 cache misses called for a DRAM access. The solution was a second level of cache: a small amount of SRAM residing on the system bus. SRAM is much faster than DRAM, but many times more expensive. However, this caused L1 cache misses to be much less painful.

With the Pentium II, L2 cache moved off of the system bus, and onto a faster, independent bus. Then, with the arrival of the Penitum !!! (Coppermine) and the AMD Thunderbird Athlon, the L2 cache moved onto the CPU die itself, and became really nothing more than a larger L1.