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Acronym for error correcting code or error checking and correcting. It increases memory latency and decreases memory bandwidth, but increases reliability, an acceptable tradeoff in many applications. It consists of three levels: error checking (EC), error checking and correcting (ECC), and error checking and correcting with scrubbing (ECC Scrub).

EC uses single-bit parity. It merely checks to see if there is an error. It does not correct any that it finds. It is the simplest and fastest method.

ECC uses multiple-bit parity. It checks for errors and corrects any it finds. It is more complex and slower than EC, but more reliable.

ECC Scrub is basically ECC with one additional characteristic: it completely refreshes the memory after each correction.

ECC-capable memory is easily identifiable in memory specifications as being one bit per byte bandwidth greater than the bandwidth of the memory controller. For example, a 256MB DDR SDRAM DIMM might be labeled as either 32Mbx64 or 32Mbx72. The former does not have ECC; the latter does. The extra byte represents the extra chip necessary for parity bits. This makes ECC memory slightly more expensive, by about 2-5 United States cents (U.S.-centric, I know) per megabyte at current prices.


  • Tyan Thunder K7 S2462 manual (Tyan document part # D1441-100)
  • http://www.crucial.com/store/listmodule.asp?module=DDR+PC2100&Attrib=Package
  • Ars Technica's technical blackpapers on memory technologies
  • http://www.corsairmicro.com/main/tecc.html

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