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While Uni of California worked on RISC the original MIPS project was developed at Stanford. MIPS stands for Microprocessor without Interlocked Pipeline Stages. RISC and MIPS are both based on the principle software and hardware design must be done together to achieve best performance. They have proved very popular (SPARC, PowerPC, LSI), however Intel are a good example of the opposite of MIPS and have increased instruction set complexity with each revision of processors.

Back to the principle. A smaller amount of simple instructions which can be implemented with a degree of parallelism is more efficient than providing large and complex hardware instructions which are rarely (if ever) used by compilers. More instructions are required in software so code density is sacrificed for simplicity (& hence ability to parallelise and increase speed).

Some MIPS standards: MIPS-I is the original instruction set architecture (ISA). Other standards e.g. MIPS-II adds multiprocessor sync, MIPS-III adds 64-bit addressing & data & more floating point instructions, MIPS-IV prefetch & high perf floating point, MIPS-V SIMD (Single Instruction Multiple Data) floating point (for supercomputing/gfx).

The MIPS-16 extension provides a compressed instruction set (reduces memory requirements).

rs = source register, rt = target register
MIPS-16 Instruction |opcode 5|rs 3|rt 3|value 5| 5+3+3+5 = 16 bits, 8 registers
MIPS-I Instruction |opcode 6|rs 5|rt 5|value 16| 6+5+5+16 = 32 bits, 32 registers

RISC/MIPS cache memory to allow for instructions to minimise slower external memory access. This allows each stage of pipeline instructions to execute each step (including cache memory/read or write) in one clock cycle. MIPS 5 stage pipeline is as follows: IF Fetch instruction from cache, RD Read registers, ALU Arithmathic/Logic Unit operation, MEM read/write memory (to cache), WB Write registers.

 Pipe1 Instr1  IF  RD  ALU MEM WB 
 Pipe2 Instr2      IF  RD  ALU MEM WB 
 Pipe3 Instr3          IF  RD  ALU MEM WB 
 Pipe4 Instr4              IF  RD  ALU MEM WB 
 Pipe5 Instr5                  IF  RD  ALU MEM WB 
 Pipe1 Instr6                      IF  RD  ALU MEM WB 
 Pipe2 Instr7                          IF  RD  ALU MEM WB 
   ..    ..                                 .        .
   ..    ..                                   .        .

Some MIPS-I/II registers. Registers are used and named according to conventions.

     zero   $0
     at     $1        assembler temporary
     v0-v1  $2-$3     values returned by subroutine
     a0-a3  $4-$7     values passed to subroutine (arguments)
     s0-s7  $16-$23   subroutine variables
     sp     $29       stack pointer
     ra     $31       return address

Some instruction examples, a flavour of MIPS assembly

8FA30024, LW $v0,144($sp) # v0 = *(sp+144), Read from address (sp + 144)
AC430000, SW $v1,0($v0)   # *(v0+0) = v1,   Write to address (v0 + 0)

# Masking example
40036800, MFC0 $v1,$13(0)           # Read from CP0 register 13
2402047C, ADDIU $v0,$zero,0x47C     # v0 = 47c
00621824, AND $v1,$v1,$v0           # v1 = v1 & v0
24020400, ADDIU $v0,$zero,0x400     # v0 = 400 (ADD Immediate (U = no exception)

# Note the use of NOPs or of useful instructions.
# They used after branch/jump instructions.
# Due to pipelining  a branch takes 2 stages

# Conditional branch
1443001C, BNE $v0,$v1,112           # Branch to pc + 112 if (v0 NE v1)
00000000, NOP                       
# Subroutine return                 
03400008, JR $ra                    
3442000A, ORI $v0,$v0,0xA           # Store subroutine return value $v0 = 000a  

# Load two addresses, copy 32-bit word from one to other
# Note it takes 2 instructions to load 32 bit address
# Note it takes 5 instructions to read & write memory
3C0219FF, LUI $v0,0x19FF            # $v0 = 19ff0000  
3442FF00, ORI $v0,$v0,0xFF00        # $v0 = 19ffff00  
3C035049, LUI $v1,0x5049            # $v1 = 50490000  
3463430A, ORI $v1,$v1,0x430A        # $v1 = 5049430a  
AC430000, SW $v1,0($v0)             # *(19ffff00+0) = *(5049430a)