Pred`i*ca"tion (preh' dih kay' shuhn), n.
3.
The
conditional execution of an instruction.
In deeply pipelined architectures such as Texas Instruments' C6000 (DSPs) and Intel's P6 (Pentium III processors) and IA-64 (Itanium processors), branches and jumps have so many delay slots (or, in machines with interlocked pipeline stages, so much penalty for misprediction) that you don't want to branch except when absolutely necessary. Predication avoids many branches by executing a given instruction if and only if a given register is (non)zero, eliminating a large fraction of branches entirely and making basic blocks larger. BIG speed win.
For example, C6000-series processors can conditionally execute an instruction based on the zeroness of register A1, A2, B0, B1, or B2, denoted by a prefix in square brackets before the instruction. The common instruction
[b0] sub .s2 b0, 1, b0
uses the S2
functional unit to
decrement the B0 register if it's not already 0. (To specify execution if a register IS zero, use a
bang to take the
logical NOT: [!b0] instead of [b0].)
A related optimization technique, speculation, executes both paths of a branch simultaneously in a branch's delay slots; the code after the branch adjusts the results as necessary, discarding "wrong" answers.
For an explanation of features that lessen the impact of branches on newer architectures, see http://developer.intel.com/software/products/compilers/f50/fitanium_unique1.htm