LOCOS (LOCal Oxidation of Silicon) was for decades the most widely-used method for isolating transistors in an integrated circuit (IC). In the past few years shrinking transistor spacings have forced IC companies to begin a transition from LOCOS to shallow trench isolation. Still, LOCOS is the most cost-efficient isolation method for most integrated circuits, and it is interesting for historical and didactic reasons.
The need for transistor isolation
An integrated circuit can contain up to hundreds of millions of interconnected transistors (MOSFETs). The body and channel of these transistors are made from the top of a silicon wafer. A thin insulating layer (presently polycrystalline silicon dioxide, better known as glass) is grown on top of the silicon wafer. A conductive gate (presently polysilicon) is deposited on top of the insulating layer. A voltage applied to the gate acts to change the conductivity of the channel beneath it.
In the diagram below I will give a rather specific and silly, but easy-to-draw example that shows the necessity of an isolation technique. The diagram shows two adjacent MOSFETs which are intended to be unconnected. Assume that the sources and drains are connected to other transistors or power supplies in the circuits (for simplicity these connections aren't shown). An interconnect wire that isn't part of the two MOSFETS passes between them.
_________ ______ _________
| | | | | |
| Gate 1 | | Wire | | Gate 2 |
| | | | | |
|_________|_____|______|______|_________|
| |
| Thin insulator |
______|_________ _____________________________|_____
|Source| |Drain| |Source| |Drain|
| 1 | | 1 | ^ | 2 | | 2 |
|______| Body 1 |_____| | |______| Body 2 |_____|
|
Parasitic
MOSFET
Silicon wafer
Notice that the wire running between the MOSFETs creates a third parasitic MOSFET. The two MOSFETS that were intended to be independent can be shorted and the circuit will fail. This problem can be fixed with the following structure, which is more difficult to fabricate but has the advantage that it works!
______
| |
| Wire |
| |
_________ |______| _________
| | | | | |
| Gate 1 | | | | Gate 2 |
| | | | | |
|_________|_____| |______|_________|
| |
| Insulator |
______|_________ _____________________________|_____
|Source| |Drain| |Source| |Drain|
| 1 | | 1 | ^ | 2 | | 2 |
|______| Body 1 |_____| | |______| Body 2 |_____|
|
Highly-doped
channel stop
Silicon wafer
The problem was fixed by a combination of two solutions. First, the insulating material between MOSFETs was thickened. In the LOCOS process, this thick silicon dioxide is called field oxide. Second, the silicon between MOSFETs was doped in such a way that it is difficult to "invert" and thus difficult to short*.
* The sources/drains and the silicon wafer (or well) are of opposite doping type. If the sources and drains are n+, the wafer (or well) is p. The channel stop implant would make the region between the source and drains p+, which is harder to invert to n.
The LOCOS process
I will give a brief introduction to the LOCOS process. Given the economic importance of integrated circuits, there is much literature on this subject. One general reference is given at the end of this writeup.
The idea behind the LOCOS process is to isolate the transistors before they are fabricated. The channel-stop implantation and field oxidation are done before gate formation and source and drain implantation. After the field oxidation is done, the regions without the thick field oxide are referred to as "active areas" since they will contain transistors.
The LOCOS process is a bit counterintuitive. I will describe it and then explain the motivation. First a thin (100-200nm) layer of silicon nitride is deposited by CVD over what will become the active areas*. Then the channel-stop ion implantation is done. The silicon nitride acts as an implantation mask over the active areas. Next the field oxide is grown at around 1000 deg C for 2-4 hours, and becomes 0.8-1.0 μm thick. This oxide does not grow from the nitride--it only grows from the exposed silicon wafer. Finally, the nitride is selectively etched, and the isolation process is complete. The finished isolation structure looks a bit like the diagram below.
* Actually a thin "pad oxide" layer is grown first to provide a buffer between the stresses of the silicon/nitride interface. This layer is of technical importance only.
_ _______ __
\ / \ /
Field \ / \ /
oxide \_________/ Field \________/ Field
/ \ oxide / \ oxide
/ Active \ / Active \
_/ area \_______/ area \__
Channel
stop
The LOCOS process is self-aligned. Both the channel-stop implant and the field oxidation are patterned by the same silicon nitride layer, making them perfectly aligned to eachother. Isolation could be done in the more obvious way--pattern photoresist, implant channel-stop region, grow oxide, pattern oxide. However, this isolation method requires two lithography masks (of opposite polarity). Furthermore, no machine can align the lithography masks perfectly, so the field oxide and channel-stop regions would be misaligned. The ideal of self-aligned layers is very critical in IC fabrication.
Notice that the field-oxide growth actually consumes some of the silicon wafer, so the silicon is recessed. This is a good thing since a smoother topology improves subsequent processing steps. Also, the field oxide is not square--some oxidation occurs beneath the silicon nitride mask. The slowly tapering oxide wedge that grows underneath the nitride is known as the bird's beak because of its appearance. The bird's beak is sometimes a good thing, since it acts to smooth the topology of the wafer. However, a major problem of the bird's beak is that two adjacent birds' beaks can grow towards eachother, reducing or eliminating the active area. As lithography has improved and features have shrunk, this issue has become more severe. The bird's beak problem is one reason that IC companies must replace LOCOS in state-of-the-art integrated circuits. The most important replacement isolation process is known as shallow trench isolation.
A good reference about IC fabrication in general is the three-volume set Silicon Processing for the VLSI Era, written by Stanley Wolf.