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These curves apply to a n-channel normally-on JFET device. But the curves to other FET devices, like p-channel devices, MOSFET ones etc. have basically the same characteristics.

(In the following, I´ll refer to the gate-source-voltage as Vgs, the drain-source-voltage as Vds and the drain current as Ids.)

#### Output characteristics

```Ids  A
|                                *
|                                *
|                                *
|                               *
|                             **
Ids0+------- *********************
|      ** :
|    *    :
|  *      :
| *       :
|*        :
+---------+-------------------------------> Vds
-Vp
```
This curve was taken at a Vgs of 0V. There are three different regions:
• Triode region In the first part of the curve, the current raises approximately according to the formula Ids=Ids0/Vp^2*[(Vgs-Vp)*Vds-Vds^2].
• Saturation: The channel is now fully pinched off. Therefore, the voltage Vp is called pinch-off-voltage. It is a negative voltage because it is also the voltage that has to be applied to the gate to turn the FET off totally. The drain current is Ids=Ids0*(1-Vgs/Vp)^2.
• Breakdown: The high electric field in the channel leads to an avalanche breakdown. When the current gets too high, the FET will be destroyed.
When applying a negative Vgs, the Ids is reduced. This is due to the fact that the channel will be pinched off at a lower Vds. (Remember that it is the voltage between gate and drain that is responsible for this.) When the gate voltage drops below Vp, the channel is always pinched off, therefore from this point on there is no drain current.

The second important curve is the Vgs-Ids-curve, i.e. the curve that indicates how much gate-source-voltage leads to how much drain-current.

#### Input characteristics

```                       Ids
A
|
+ Ids0
*|
*|
* |
**  |
**    |
***       |
Vgs <------+------------+
Vp
```
This curve is taken at a Vds higher than -Vp. As noted before, Ids can be written as Ids=Ids0*(1-Vgs/Vp)^2.

This curve stops at Vgs=0 because on a JFET you can´t apply a positive voltage to the gate or the gate-source-diode will start to conduct. I´ve read that a small current through this diode lowers on-resistance a lot. Try as you like, but you know: Never believe what you read on the Internet.

On MOSFETs that have a totally isolated gate you can basically apply what you want.

On a normally-off-type, this curve begins at a Vp>0, that means that you have to apply a positive gate voltage to make the FET conduct. This is what you usually have to do with a MOSFET. (There are normally-on-MOSFETs, too, though.)

#### FET families

All FET can be put into one of four categories, depending on their channel type and if they´re normally on:
1. n-type, normally on (e.g. the aforementioned n-type JFET): Vp<0, conducts if Vgs>Vp, Vds>0, Ids>0
2. n-type, normally off (e.g. a normal MOSFET) Vp>0, conducts if Vgs>Vp, Vds>0, Ids>0
3. p-type, normally on (a p-type JFET) Vp>0, conducts if Vgs<Vp, Vds<0, Ids<0
4. p-type, normally off (a p-type MOSFET) Vp<0, conducts if Vgs<Vp, Vds<0, Ids<0
...so that means that for the p-types, the output characteristics extend to the lower left instead of the upper right like in the example. The input characterictics is inverted, too.
Thanks to whereismymind for help on triode region.

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