The Terminator

Quite possibly the world's fastest CPU when released, code-named the "T5" after Terminator 2 which featured graphics designed on Silicon Graphics systems, the MIPS R10000 (Do you sense the play on T-1000?) was released in late 1995 and was first avaliable on SGI's Indigo2 systems. It was based on much of the same technology as the short lived R8000 chipset that was designed for more scientific calculations (i.e. float point) except that the R10000 was a single chip processor and was designed to be a much more flexable chip allowing it to be used in servers, graphics development with better results.

Based on the ANDES Advanced Superscalar Architecture, the R10000 can process four (Although it actually has 5 execution units) 32-bit instructions from its 32-KB, two-way set-associative instruction cache, or I-cache per cycle. After the instructions are fetched from the I-cache, they pass through a two-stage decoder. Actual decoding takes only one stage, however; the second stage is for register renaming which allows the expansion of the R10000 register file to 64-bits but allows full backwards compatability with say, the R4400. This allows for another feature in the the R10000, out-of-order execution. The R10000 can also predict up to 4 branches of executions. This is usually right and corrected quickly should it be wrong by the fact that the processor records the stream of data prior to the error.

The processor runs internally at 200 MHz and has a dedicated 128-bit data bus between it and the cache allowing for a theoretical 3.2 Gigabyte transfer rate as well as a 200 MHz SSRAM interface.

The R10000 was discontinued in 1998 with the arrival of the R12000.

The MIPS R10000

  • 64-bit RISC microprocessor, Rx000-compatible design.
  • MIPS' first single-chip superscalar CPU.
  • Dynamic-branch prediction and speculative execution up to four levels deep.
  • Out-of-order execution.
  • Five functional units: two integer, two floating point, and load/store.
  • Executes up to five instructions per cycle, graduates (Retires) up to four per cycle.
  • 64 integer registers and 64 floating-point registers, dynamically mapped to 32 integer and 32 floating-point logical registers.
  • 32 KB, two-way set-associative instruction and data caches.
  • On-chip control for up to 16 MB of secondary cache.
  • Multiprocessor cluster bus supports up to four CPUs.
  • 200 MHz internal clock; external clock programmable for 200, 133, 100, 80, 67, 57, or 50 MHz.
  • 64-entry TLB, 44-bit virtual addressing.
  • More than six million transistors.
  • Fully static CMOS, 3.3-V, four-layer metal, 0.35-micron process.
  • Approximately 290mm2 die.
  • ANDES Advance Superscalar Architecture.
  • Avalanche Bus System Interface

Systems Utilizing the R10000

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