While Uni of California worked on RISC the original MIPS project was developed at Stanford. MIPS stands for Microprocessor without Interlocked Pipeline Stages. RISC and MIPS are both based on the principle software and hardware design must be done together to achieve best performance. They have proved very popular (SPARC, PowerPC, LSI), however Intel are a good example of the opposite of MIPS and have increased instruction set complexity with each revision of processors.

Back to the principle. A smaller amount of simple instructions which can be implemented with a degree of parallelism is more efficient than providing large and complex hardware instructions which are rarely (if ever) used by compilers. More instructions are required in software so code density is sacrificed for simplicity (& hence ability to parallelise and increase speed).

Some MIPS standards: MIPS-I is the original instruction set architecture (ISA). Other standards e.g. MIPS-II adds multiprocessor sync, MIPS-III adds 64-bit addressing & data & more floating point instructions, MIPS-IV prefetch & high perf floating point, MIPS-V SIMD (Single Instruction Multiple Data) floating point (for supercomputing/gfx).

The MIPS-16 extension provides a compressed instruction set (reduces memory requirements).

rs = source register, rt = target register
MIPS-16 Instruction |opcode 5|rs 3|rt 3|value 5| 5+3+3+5 = 16 bits, 8 registers
MIPS-I Instruction |opcode 6|rs 5|rt 5|value 16| 6+5+5+16 = 32 bits, 32 registers

RISC/MIPS cache memory to allow for instructions to minimise slower external memory access. This allows each stage of pipeline instructions to execute each step (including cache memory/read or write) in one clock cycle. MIPS 5 stage pipeline is as follows: IF Fetch instruction from cache, RD Read registers, ALU Arithmathic/Logic Unit operation, MEM read/write memory (to cache), WB Write registers.

 Pipe1 Instr1  IF  RD  ALU MEM WB 
 Pipe2 Instr2      IF  RD  ALU MEM WB 
 Pipe3 Instr3          IF  RD  ALU MEM WB 
 Pipe4 Instr4              IF  RD  ALU MEM WB 
 Pipe5 Instr5                  IF  RD  ALU MEM WB 
 Pipe1 Instr6                      IF  RD  ALU MEM WB 
 Pipe2 Instr7                          IF  RD  ALU MEM WB 
   ..    ..                                 .        .
   ..    ..                                   .        .

Some MIPS-I/II registers. Registers are used and named according to conventions.

     zero   $0
     at     $1        assembler temporary
     v0-v1  $2-$3     values returned by subroutine
     a0-a3  $4-$7     values passed to subroutine (arguments)
     s0-s7  $16-$23   subroutine variables
     sp     $29       stack pointer
     ra     $31       return address

Some instruction examples, a flavour of MIPS assembly

8FA30024, LW $v0,144($sp) # v0 = *(sp+144), Read from address (sp + 144)
AC430000, SW $v1,0($v0)   # *(v0+0) = v1,   Write to address (v0 + 0)

# Masking example
40036800, MFC0 $v1,$13(0)           # Read from CP0 register 13
2402047C, ADDIU $v0,$zero,0x47C     # v0 = 47c
00621824, AND $v1,$v1,$v0           # v1 = v1 & v0
24020400, ADDIU $v0,$zero,0x400     # v0 = 400 (ADD Immediate (U = no exception)

# Note the use of NOPs or of useful instructions.
# They used after branch/jump instructions.
# Due to pipelining  a branch takes 2 stages

# Conditional branch
1443001C, BNE $v0,$v1,112           # Branch to pc + 112 if (v0 NE v1)
00000000, NOP                       
# Subroutine return                 
03400008, JR $ra                    
3442000A, ORI $v0,$v0,0xA           # Store subroutine return value $v0 = 000a  

# Load two addresses, copy 32-bit word from one to other
# Note it takes 2 instructions to load 32 bit address
# Note it takes 5 instructions to read & write memory
3C0219FF, LUI $v0,0x19FF            # $v0 = 19ff0000  
3442FF00, ORI $v0,$v0,0xFF00        # $v0 = 19ffff00  
3C035049, LUI $v1,0x5049            # $v1 = 50490000  
3463430A, ORI $v1,$v1,0x430A        # $v1 = 5049430a  
AC430000, SW $v1,0($v0)             # *(19ffff00+0) = *(5049430a)

minor detail = M = misbug

MIPS /mips/ n.

[abbreviation] 1. A measure of computing speed; formally, `Million Instructions Per Second' (that's 10^6 per second, not 2^(20)!); often rendered by hackers as `Meaningless Indication of Processor Speed' or in other unflattering ways, such as `Meaningless Information Provided by Salesmen'. This joke expresses an attitude nearly universal among hackers about the value of most benchmark claims, said attitude being one of the great cultural divides between hackers and marketroids (see also BogoMIPS). The singular is sometimes `1 MIP' even though this is clearly etymologically wrong. See also KIPS and GIPS. 2. Computers, especially large computers, considered abstractly as sources of computrons. "This is just a workstation; the heavy MIPS are hidden in the basement." 3. The corporate name of a particular RISC-chip company. 4. Acronym for `Meaningless Information per Second' (a joke, prob. from sense 1).

--The Jargon File version 4.3.1, ed. ESR, autonoded by rescdsk.

MIPS stands for Microprocessor Without Interlocked Pipeline Stages and is also a spoof on the stupid benchmark of the same name. The now ubiquious chip was developed as a project at Stanford University and has headed by Professor John L. Hennessy (Now president of Stanford.).

The Company

MIPS Computer Systems Inc. was the commercialization of the Stanford University VLSI project from the early 1980s that created the processor of the same name. The company was created by several of the MIPS Project founders, including Professor John L. Hennessy around 1984. The company was the first RISC processor company since IBM. Soon after its founding, MIPS released its first processor, the 32-bit RISC MIPS R2000 and made a good profit, with its first client being UK based, Whitechapel Workstations. Eventually, it became the sole producer of Silicon Graphics (SGI) who dropped its Motorola processors for their chips and would eventually aquire MIPS in 1992 when MIPS ran into extreme financial hardship.

After the aquisition MIPS became the MIPS Technologies subsidary of SGI and the MIPS operated as much as it had before the aquisition. However, with the arrival of the Rick Belluzzo, the profitable emmbeded chip section of MIPS was divested into today's MIPS Technologies. The rest of the MIPS division, especially the R1x000 design team remained with SGI and continues to produce the chips that SGI uses for their processors.

Today MIPS Technologies is doing exceedingly well most embedded systems are based on MIPS processors...the Playstation 2, cable boxes and many other things. It's success is amazing considering the trouble its former owner is in. MIPS Technologies is based in (Big surprise) Mountain View, California.

* MIPS is copyright MIPS Technologies Inc.

When Shigeru Miyamoto and his team were working on Super Mario 64 for the Nintendo 64 one of the first things they created was a blank, featureless level in which Mario had to chase and capture a yellow rabbit. This level was used to test the 3D Mario model and to work out the controls for the upcoming game. Like Miyamoto's Penguin, the little rabbit struck a chord with the development team and they decided to place him in the finished game. Down in the castle basement Mario encounters the rabbit where he must chase and capture him. Doing so will earn Mario a star. The rabbit's name? Mips, after the CPU chip.

In 2004 Nintendo upgraded Super Mario 64 for the Nintendo DS handheld system. In the new Super Mario 64 DS Mips returns with a cadre of rabbit brothers who give up keys to unlock mini-games when caught. These new rabbits are multicolored, but all of them are based on the original Mips design.

Super Mario 64 Player's Guide
Nintendo Power interview with Shigeru Miyamoto in 1996

Log in or register to write something here or to contact authors.