Background: VLIW, or Very Long Instruction Word, is a class of RISC architectures in which an instruction packet specifies what multiple functional units will be doing during a given cycle. For this reason, it is also known as EPIC, or Explicit Parallel Instruction Computing. A drawback in early VLIW was that binary code became bloated with NOPs as not enough parallelism could be found to fill all units all the time.
VelociTI, used in Texas Instruments DSP chips, decreases code size by breaking each packet of eight instructions (called a "fetch packet") into several "execution packets" of instructions that can be executed in parallel. For example, a fetch packet {load, load; add, load; add; multiply; store, nop} would be broken into execution packets {load, load}, {add, load}, {add}, {multiply}, {store, nop}. There are eight functional units in the processor; only one can get an instruction in a given execute packet. An execution packet may not cross fetch packet boundaries (except on the more expensive C6400 parts), and branches always go to the beginning of a fetch packet, but the NOP-padding at the end of an execution packet does not affect performance because those NOPs are executed in parallel with the last execution packet.
IA-64's version of EPIC does something similar but subtly different. Its fetch packets are only three instructions long, but execution packets can cross fetch packet boundaries, and instructions do not explicitly state which functional unit to use, allowing a particular implementation to determine whether to execute a packet in one, two, or more cycles.
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