testability

Put another way; a more 'testable' design means that less of its potential faults are undetectable.

In order for any given circuit fault to be detectable, we need to be able control the state of the circuit such that it is sensitised to the fault. Additionally, we need to be able to observe the effect of the fault on the circuit's operation.

Simple Example: 2-Input NAND Gate

  A B | Y
  ----|---
  0 0 | 1
  0 1 | 1
  1 0 | 1
  1 1 | 0

Where: A, B are input's, Y is the output.

Consider the case where there is a fault on input A such that it is 'stuck-at-0', i.e. short-circuited to a voltage level representing a logical '0'. Also, assume for now that we have direct access to all three of the NAND gate's pins. Let's look at the two factors which determine testability:

Controllability: Can we sensitise the circuit such that the fault will cause a change in the expected behaviour of the circuit? With reference to the truth-table, we can see that driving both inputs 'high' should give a logic 'low' on the gate's output, (line 4). However, with input A 'stuck-at-0', the NAND gate will behave as per line 2 of the truth-table. the output, Y, will be different to what was expected.

Observability: Since we have direct access to all the gate's pins in this simple example, we have achieved 'observability' by definition.

As you can see, a 'stuck-at-0' fault on input A is testable in this example.

What if the NAND output, Y, is connected to the input of another 2-Input NAND? Perhaps we don't have direct access to the output of the first NAND gate any more - we now have a small observability problem.

What if one or both of the original NAND gate's inputs are not directly reachable? Say they are driven by other logic gates? We have a controllability problem.

Hopefully, you can see how ensuring testability of even a simple logic gate can be a difficult task when it is deeply embedded within an IC.