Metastability is a term used in digital electronics. It describes a specific problem you can get when using an asynchronous signal.

Warning: This writeup is quite technical. If you don't understand this, don't worry. If you want to understand it, I suggest you read more about digital design, flip-flops and electronics. :) Sleeping wolf's digital circuit design metanode will be a good starting point for this.

In a synchronous design, all signals are sampled into storage elements - "flip-flops" or "registers" - at a specific time, decided by a common timing signal called a clock. When the clock goes high (assuming positive clock), all register inputs should be stable at either logical 1 or logical 0.

Metastability may occur if the input to a flip-flop changes just as the clock goes high. Neither logical level is read into the register; instead, the register output will be completely unpredictable, changing rapidly between 0 and 1. The output is in a metastable state.

Modern flip-flops
In practice, metastability as described above does not occur in modern flip-flops. They are made so that the output always stays at a specific level; metastability only occurs inside the flip-flop. Unfortunately, this doesn't solve the problem completely. Metastability inside a flip-flop may cause the output to change between two clock ticks. Depending on delay to next memory elements, this can cause the signal to be read differently at two other places in the chip, leading to errors.

How to avoid metastability
Metastability is avoided by keeping to a strict, synchronous design. If all changes are caused by the clock, metastability will not take place. If you have to use an asynchronous signal, synchronise it to your clock first. Normally, two registers are used for this, placed serially (one after the other). If metastability happens in the first flip-flop, like described above, it will only spread to the next synchronising flip-flop. Chances are very slim that the metastable signal changes at the exact moment needed to make metastability in the next flip-flop as well.

In applications where stability is very important, more synchronising flip-flops may be inserted. This will increase the latency of the synchronised signal (more clock cycles are needed before a change will propagate through the synchronisation), but drastically decrease the chance of metastability.

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