S-100

Also called the Altair bus, this was a 100-pin bus system used in the Altair 8080, IMSAI 8080 and ultimately in most other hobbiests' computers of the 1970s and early 1980s. Reputedly very difficult to work with, very demanding of a steady soldering arm.

S-100 (Altair bus) pinout:

1

+8v

unregulated 8v power supply

2

+16v

unregulated 16v power supply

3

XRDY

causes CPU to enter wait state

4

VI0

vectored interrupt 0

5

VI1

vectored interrupt 1

6

VI2

vectored interrupt 2

7

VI3

vectored interrupt 3

8

VI4

vectored interrupt 4

9

VI5

vectored interrupt 5

10

VI6

vectored interrupt 6

11

VI7

vectored interrupt 7

12

(no use)

13

(no use)

14

(no use)

15

(no use)

16

(no use)

17

(no use)

18

STADSB

3 state status line cpu buffer

19

CDSB

3 state command line buffer

20

UNPROT

Clears PROTECT flip flop of board

21

SS

Single step occurring in cpu

22

ADDDSB

3 state address line

23

DODSB

3 state data line

24

02

cpu phase 2 clock

25

01

cpu phase 1 clock

26

PHLDA

cpu ack DMA hold

27

PWAIT

cpu ack wait state

28

PINTE

cpu indicates interrupts enabled

29

A5

address bit 5

30

A4

address bit 4

31

A3

address bit 3

32

A15

address bit 15

33

A12

address bit 12

34

A9

address bit 9

35

D01

data line output 1

36

D00

data line output 0

37

A10

address bit 10

38

D04

data line output 4

39

D05

data line output 5

40

D06

data line output 6

41

DI2

data line input 2

42

DI3

data line input 3

43

DI7

data line input 7

44

SMI

cpu fetching instruction

45

SOUT

cpu output cycle

46

SINP

cpu input cycle

47

SHEMR

cpu in memory read cycle

48

SHLTA

cpu halted for DMA

49

CLOC

buffered 2mhz clock for board use

50

GND

Ground

51

+8v

identical to pin 1

52

-16v

unregulaged -16v power

53

SSWSB

sense switch disable

54

EXTCLR

clear front panel

55

(no use)

56

(no use)

57

(no use)

58

(no use)

59

(no use)

60

(no use)

61

(no use)

62

(no use)

63

(no use)

64

(no use)

65

(no use)

66

(no use)

67

(no use)

68

MWRT

write data out bus to memory

69

PS

protect memory

70

PROT

set memory protect flip flop

71

RUN

cpu not in single step mode

72

PRDY

not in wait state

73

PINT

interrupt request

74

PHOLD

hold state occurs

75

PRESET

system reset

76

PSYNC

new machine cycle begins

77

PWR

write output bus data to memory or i/o

78

PDBIN

input data bus to cpu

79

A0

address line 0

80

A1

address line 1

81

A2

address line 2

82

A6

address line 6

83

A7

address line 7

84

A8

address line 8

85

A13

address line 13

86

A14

address line 14

87

A11

address line 11

88

D02

output data line 2

89

D03

output data line 3

90

D07

output data line 7

91

DI4

data input line 4

92

DI5

data input line 5

93

DI6

data input line 6

94

DI1

data input line 1

95

DI0

data input line 0

96

SINTA

cpu ack interrupt

97

SWO

write to memory or i/o

98

SSTACK

address bus contains stack address

99

POC

power on clear and reset

100

GND

ground