Silicon On Insulator

Silicon-On-Insulator (SOI) devices were developed to combat some limitations of conventional CMOS. SOI provides better performance than conventional CMOS in several areas such as speed, insulation from environmental factors, high-temperature functionality, and allows the option of fully depleted (FD) devices.

An SOI device looks and functions much like a conventional CMOS device. The largest difference is the reduction in silicon junction area, which provides some of the advantages mentioned previously. Where there was only bulk silicon in the traditional CMOS device, the SOI device contains the same silicon situated on an insulator, hence the name Silicon-On-Insulator. A common insulator for this purpose is SiO2.

SOI is one of several extensions of conventional CMOS, along with Dual-Gated Devices and SiGe. These are evolutionary advancements, intended to correct certain short-comings of the conventional CMOS that they are based on.

SOI seeks to minimize short-channel effects, making it easier to compress the size of a device and enhance speed performance. SOI also provides complete insulation against interference from other devices, making high density packing a reasonable goal.

Full depletion, which can only be fabricated in dielectrically isolated silicon, provides the following advantages:

• reduction of source/drain parasitics (i.e., increased speed)
• higher output current
• reduced hot-carrier effects
• reduced short-channel effects

Complete Isolation
• Complete isolation of closely spaced components provides freedom from latch-up which plagues closely-spaced devices in bulk silicon; in addition to the elimination of latch-up, complete isolation enables closer spacing and thus higher packing densities.
• The support of the thin silicon on a dielectric substrate results in field distributions which are associated with reduction of short-channel effects.
• The complete dielectric enables high voltage operation, and the isolation of high voltage components as, for instance, in “smart power” devices.
• The support of the silicon thin film by the dielectric reduces the source of yield loss in the SOI materials systems in which the insulating support is thick (the extreme case of this being the silicon on sapphire substrate).

Reduced junction area
• Reduced junction area is the key to radiation hardness since degrading single event upset (SEU) and dose rate effects occur at, or near, junctions.
• Reduced junction area provides reduced capacitance, and associated increase in device speed and decrease in dynamic power consumption.
• Reduced junction area provides relatively high temperature device performance.

Fully depleted devices
• Fully depleted devices are enabled by the availability of thin silicon supported by a dielectric substrate; these devices cannot be fabricated in bulk silicon.