CMOS stands for Complementary Metal Oxide Semiconductor. its a little chip inside a PC that stores date and time, it also stores harddrive types etc. If you go to the BOIS settings at powerup before POST you will be able to view your CMOS settings and also Save to CMOS and exit

CMOS is much more than a little chip in your PC. It is a digital logic family considered to be a big improvement over previous logic families such as TTL, RTL, and ECL.

CMOS works over a very wide power-supply range, uses no power when inputs are stable (not changing), and very little otherwise.

Since CMOS is relatively tolerant of system noise (and is itself almost noiseless), is inexpensive and is available from dozens of manufacturers, it is a good choice for digital logic design both in industry and for the hobbyist.
The CMOS, (Complementary-MOS), logic family is so called because it uses both N-type and P-type MOS transistors to create logic functions.

The simplest example of a CMOS circuit is that of a logical inverter:

                               ---    VDD
                      -------| PMOS
                      |      |--
                      |         |
                      |         |
           IN --------|         |--- OUT
                      |         |
                      |         |
                      |      |--
                      -------| NMOS
                                -      VSS
Here, the input is connected to the gate of both the PMOS and NMOS transistor. VDD represents the positive voltage supply, VSS represents the zero volts line.

Here's how it works:Applying a 'logical 1' voltage level to the input causes the PMOS device to turn off and the NMOS device to turn on. Current flows through the NMOS transistor only, and the inverter's output is pulled down to VSS, (a 'logical 0' voltage level or zero volts). Thus, a 'logical 1' on the input causes a 'logical 0' to appear on the output - an inversion of the logical state of the input to the device. The same theory applies with a 'logical 0' on the input.

This simple logic gate illustrates one of the main benefits of using CMOS logic - when the PMOS device is 'on', the NMOS device is 'off', and vice versa. Thus, the only time there is a current path between VDD and VSS is during the brief period where the states of the transistors are switching.

Withnails writeup is correct, but one very important problem of CMOS is not mentioned:
PMOS transistors turn on if there is a positive voltage difference between source and gate at a certain level and NMOS turn on if the difference is negative. This implies that PMOS transitors are only good swichtes when using VDD as source and NMOS are only good switches for VSS - if e.g. PMOS is used with VSS it uses the other pin as reference. However, this voltage on this pin is pulled down and when it has reached a certain level > 0, the transistor turns off. So the output is not pulled down at VSS but a slightly higher level. If you put several such transistors in a row (connecting the output to the gate of the next transistor) you would get totally screwed up voltage levels.

Therefore PMOS are usually used as switches to VDD and NMOS to VSS. This gives most basic gates an "inverting" character: You can only get a logical 1 output with logical 0s at the gates of the PMOS transistors and a logical 0 is produced by logical 1s at NMOS transistors. It is not possible to build an AND or an OR by just on stage of transistors, you must always put some in a row or use inverters.

Another effect is that some standard logic gates become very asymmetric. Let's take an NOR as an example:

                    ___ VDD
       +------------|   PMOS transistor
       |             |
       |       +----|   PMOS transistor
 in B -+       |     |
       |       |     +------------------- out
       | in A -+     |
       |       |  +--+---+
       |       |  |      |
       |       +-|    +-|   2 NMOS transistors
       |          |   |  |
       |         ---  | ---
       |         VSS  | VSS
This would be a standard implementation of a NOR2, it computes out = not(A or B). The path from VDD to out has 2 transistors in series, the path from VSS to out 2 transistors in parallel. As you might expect, switching out from logic 1 to 0 would be faster than switching from 0 to 1. (same speed PMOS and NMOS transistors assumed). For a NOR2 this would be not problematic, but imagine larger gates like a NOR100 !. The are several tricks to get around this, e.g. dynamic logic.

Electrical engineers would point out that the upper explanation is not 100 percent correct, but I find this one easiest to understand. The effect of bad switch against VDD/VSS can also be explained by lots of calculation with equations describing the behavoir of a transistor.

Why do we use CMOS?

The logic functions implemented in CMOS circuits could be designed with just one half of the circuit. Look at the CMOS circuits in the writeups above: the logical gates that are represented could very easily be achieved by using the bottom half of the circuit only. The pull-up part of a CMOS circuit (the part on top, above the "out" gate) is the inverse of the pull-down part. The reason CMOS is used is because the power dissipated by the circuit, and thus the heat generated by it, is greatly reduced. It may not be readily apparent why this is the case. Adding more transistors would, at first glance, seem to increase the power dissipated.

However, consider the fact that the pull-up and pull-down portions of the circuit are inverse functions. If the pull-up is a NAND, then the pull-down is an OR. If you feed the same inputs to both parts, invariably one will be low (outputting a 0) and one will be high (outputting a 1). As a result, at least one portion of the circuit will be acting as an open circuit. The voltage present at the drain will have no path to ground, so only a negligible amount of current will ever be present in the entire circuit.

One way to model MOSFETs as linear elements is to look at them as if they were resistors when they are on, and as open switches when they are off. If the circuit were just composed of the pull-down portion, a ton of current would flow through that resistor whenever the MOSFET was fed a high voltage (logical 1). Looking at the FET as a resistor with one side attached to ground and one side attached to the drain voltage, Ohm's Law tells us that current with magnitude = (drain voltage) / ((ON resistance of MOSFET) + (Load resistance)) will flow through. Power is equal to current times voltage, so you will get a significant power here, which is known as static power.

If we've come up with an ingenious method of eliminating this static power, why do circuits like microprocessors produce heat at all? In addition to static power, there is dynamic power. Every MOSFET has a small parasitic capacitance at its drain. This is simply a result of its imperfection in production. When MOSFETs switch from on to off and back again, charge builds up on that imaginary capacitor. When the capacitor discharges, some power is dissipated over the present resistors, thus producing dynamic power.

There are BIOS routines to talk to other common devices that are more likely to be changed. These changeable hardware devices include such things as:
Hard Drives
Floppy Drives
The BIOS routines for these devices are also stored on the ROM chip. However, if we change one of these items, such as upgrading a hard drive or adding a second hard drive, certain parameters must be changed to reflect the modifications to the hardware. We cannot change the BIOS routines on the ROM, so we need to add another type of storage chip that can be modified to reflect these changes. This changeable chip is called the CMOS (Complimentary Metal-Oxide Semiconductor) chip. In the PC world, CMOS chips do not store programs, they only store data that is read by BIOS to complete the programs needed to talk to changeable hardware. The CMOS chip also acts as a clock to keep the date and time.

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