display | more...

On PowerPC architecture, the "eieio" instruction is used enforce instruction execution in order, that is, to prevent the pipelines from executing instructions in a different order than they were intended, typically used in combination with instructions that are doing memory mapped I/O. I've heard (and it sounds reasonable, but I don't know for sure that it's true) that the opcode used for the eieio instruction is the same as a NOP on earlier versions of the processor that didn't have the capability to execute instructions in parallel. That is, they made the NOP instruction do something on the PowerPC.

A PowerPC ISA instruction meaning "Enforce In-Order Execution of I/O". This is different from the sync instruction, which also flushes the instruction pipeline, or the isync instruction which only serializes execution.

eieio waits for all memory operations to complete before initiating any new ones. This prevents a processor from modifying a mutex'd structure until it's seen as locked by all others in the computer.

It does not wait for previous instructions to complete. That's what isync is for.

I doubt that there ever was a nop instruction on PowerPC or POWER, and if there were, it wouldn't be used for this. eieio is a pretty specialized function usually seen in implementations of multiprocessing APIs in operating systems. nop on PowerPC is ori r0, r0, 0. It's RISC, so they don't like to assign new opcodes willy-nilly (although I don't know the difference between sync and eieio isync).

Log in or register to write something here or to contact authors.