PowerPC 603

The PowerPC 603 was the second (1994) implementation of the PowerPC microprocessor architecture, and especially designed for low-power and embedded applications. Unlike the PowerPC 601, the 603 was a complete redesign, not based on IBMs POWER processors. It thus belongs to the "G2" generation of PowerPC CPUs.

The main performance bottleneck of the 603 are the small on-chip caches which make it slower than the 601. This problem was fixed with the 603e.

Summary of features:

• 32-bit PowerPC implementation, 32- or 64-bit data bus, 32-bit address bus
• up to 80MHz clock speed
• five execution units: one integer unit, one floating-point unit (with a single precision multiply-add pipeline), one branch processing unit, one load/store unit, one system register unit
• 6-stage instruction prefetch queue
• two 8KB 2-way set-associative on-chip instruction and data caches
• memory management unit with two 64-entry 2-way set-associative instruction and data translation look-aside buffers; the tablewalk is implemented in software
• not designed for multiprocessing and only supports the MEI subset of the MESI protocol for maintaining cache coherence with DMA devices
• three special power management modes: doze, nap and sleep