RISC

RISC chips understand fewer, but more generalized, instructions than their CISC counterparts. RISC is currently recognized as the correct way to do good CPUs by everyone but Intel, it seems.

While RISC chips have to process more instructions than a CISC chip would need to do the same thing, they can process them faster because of smaller lookup tables. RISC chips include: PowerPC, Alpha, SPARC, PA-RISC, MIPS.

RISC stands for "Reduced Instruction Set Computer". Originally, the idea was to make microprocessor chips that were less complex, so that they could be built smaller and run faster. Each instruction would take just a fraction of the time to execute, but more instructions would need be executed to accomplish the same task.

Although this might make things less convenient for the assembly language programmer, it was much simpler for a compiler to use effeciently. Indeed, this was the sort of thing that the designers of RISC were aiming for.

In addition to having fewer instructions, RISC chips supported some other interesting features. For example, all of their instructions are fixed-width.

As time as progressed, more and more instructions have been added to "RISC" chips, so that the original name is no longer accurate. Indeed, perhaps the only defining characterisitc betwen CISC and RISC chips these days is the fact that RISC chips use fixed-width instructions, while CISC chips use variable-width instructions.

RISC chips include such things as the Alpha, Power PC, and MIPS families.

A RISC chip primarily achieves its instruction reduction through forcing all data to be in registers. Whereas a CISC chip has several different versions of the ADD instruction, depending on where the data is coming from (or going to) registers or main memory.
So, instead of just getting away with with providing pointers to two numbers you wish to add together, you are forced to explicitly load the data into registers, and then execute the addition.
The RISC model is not neccessarily faster than the CISC model, however, the design of a RISC chip is far simpler. And if it's simpler, the design's less likely to break when pushed harder; as well as being significantly cheaper to manufacture using more expensive fabrication methods.
Interestingly enough, where RISC architectures make operations register based, the JVM, by going in the OPPOSITE direction, and doing away with user-accessible registers, also achieves a reduced instruction set. However few out there would DARE refer to a Java machine as RISC.

What really defines a RISC chip isn't the number of instructions, it's orthogonality and reduced interdependance. This allows the chip to make much better use of pipelining and having parallel math or execution units.

In fact, the RISC paradigm has proven to be so successful in this regard that modern i386 chips translate their CISC instructions to an internal RISC command set before execution. Even though this requires a lot of additional effort and doesn't yield the full benefits, the chips are faster than they would be without it.

Our CPUs would probably be 3 to 5 times more powerful today if the research effort that has been put into squeezing more performance out of the inferior i386 architecture had instead been used for making better RISC chips.

RISC - Reduced Instruction Set Computer

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History and Basic Design

RISC was the general concept of CPUs that were deveoped in the late 70s and early 80s in several different projects that resulted in Stanford's MIPS, Berkeley's RISC 1 & 2 and the IBM 801. All RISC processors share several key elements being:

• One Cycle Execution Time: RISC processors have a CPI (clock per instruction) of one cycle.
• Pipelining: A techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
• Large Number of Registers: RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory.

RISC processors concentrate more on the software and as their name states, they have a reduced assembly language instruction set.

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RISC vs. CISC

Today RISC is generally felt to be the right way to design processors. In fact, the i386 family are the last (at least major) CISC based processors.

CISC based processors take more into account of trying to get the job done in assembly in as few lines as possible. This may have been the more practical up until the 1960s. Now with much better compiler design, RISC is the way to go. In fact, in his book Only the Paranoid Survive, Andrew Grove wrote that the only reason Intel has not fully gone with RISC is because of compatability issues.

CISC

• Emphasis on hardware
• Includes multi-clock
• Memory-to-memory: "LOAD" and "STORE" incorporated in instructions
• Small code sizes, high cycles per second
• Transistors used for storing complex instructions

RISC

• Emphasis on software
• Single-clock, reduced instruction only
• Register to register: "LOAD" and "STORE" are independent instructions
• Low cycles per second, large code sizes
• Spends more transistors on memory register