A type of counter implementation where the output of each bit causes the next most significant bit to either count or not count. This is used for counting numbers that are based on binary sequences such as binary or BCD.
```        +---+
+---|J Q|---+-Q3
+---|K  |   |
| +-|>  |   |             +---+
| | +---+   +-------------|AND|
+-|-------+ +-------------|   |
| +---+ | |     +-------|   |---TC
+-|-|J Q|-+-+-Q2  |  +----|   |
+-|-|K  |         |  | +--|   |
| +-|>  |   +-----+  | |  +---+
| | +---+   |        | |
+-|-------+ |        | |
| +---+ | |        | |
+-|-|J Q|-+-+-Q1     | |
+-|-|K  |            | |
| +-|>  |   +--------+ |
| | +---+   |          |
+-|-------+ |          |
| +---+ | |          |
+--|-|J Q|-+-+-Q0       |
+--|-|K  |              |
|  +-|>  |              |
|  | +---+              |
+-----------------------+
|                    |
clk                  ENT
```
Here, we are counting a 4-bit binary code for as long as the "enable toggle" (ENT) input is asserted. The Q output of the previous stage determines whether or not the JK Flip-Flop in the next state will toggle or not, with one toggle per clock pulse. The output number appears on Q3-Q0.

This device is also a ring counter, as it will reset its count back to 0000 after counting 1111, forming an infinite loop.

Upon reaching 1111, the AND causes "terminal count" (TC) to be asserted if ENT is also asserted. By connecting this TC to the ENT on another ripple counter we can extend this scheme beyond 4 bits--the next ripple counter simply becomes bits 4-7.

Sorry, this doesn't work as expected.

I think with above circuit the sequence of would go like this from cycle
to cycle, assuming ENT is on all the time:
(Q3,Q2,Q1,Q0)
( 0, 0, 0, 0)
( 0, 0, 0, 1) (ENT toggles the least significant bit on)
( 0, 0, 1, 0) (Active Q0 toggles the next bit Q1 on, and ENT toggles Q0 off)
( 0, 1, 1, 1) (Active Q1 togles Q2 on, Q1 stays as it is (because Q0=0), and ENT toggles Q0 on)
( 1, 0, 0, 0) (Q2 toggles Q3 on, Q1 toggles Q2 off, Q0 toggles Q1 off, and ENT toggles Q0 off)
( 1, 0, 0, 1) (ENT toggles Q0 on)
( 1, 0, 1, 0) (Q0 toggles Q1 on, ENT toggles Q0 off)
( 1, 1, 1, 1) (Q1 toggles Q2 on, ENT toggles Q0 on)
( 0, 0, 0, 0) (Q2 toggles Q3 off, Q1 toggles Q2 off, Q0 toggles Q1 off, and ENT toggles Q0 off)

So with these four flipflops we get just a cycle of eight, instead of maximum 16.

If you instead want a normal binary sequence
(0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111)
you should connect logical 1 to both J & K-inputs of each flip flop,
the master CLK to the first (the least significant) JK-flipflop's CLK-input,
and the inverted Q-output of each flipflop to the CLK-input
of the next flipflop.

That way each JK-flipflop is "primed permanently for toggling",
but the flip-flops 1-3 will toggle only when the preceding
flip-flop changes its state from 1 to 0. (Which will show as
a rising clock edge at the next flip-flop's CLK-input).

(To increment a binary number by one: complement all bits from
the least significant end UP TO and INCLUDING the first zero
encountered. But no further!)

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