A type of counter implementation where the output of each bit causes the next most significant bit to either count or not count. This is used for counting numbers that are based on binary sequences such as binary or BCD.
```        +---+
+---|J Q|---+-Q3
+---|K  |   |
| +-|>  |   |             +---+
| | +---+   +-------------|AND|
+-|-------+ +-------------|   |
| +---+ | |     +-------|   |---TC
+-|-|J Q|-+-+-Q2  |  +----|   |
+-|-|K  |         |  | +--|   |
| +-|>  |   +-----+  | |  +---+
| | +---+   |        | |
+-|-------+ |        | |
| +---+ | |        | |
+-|-|J Q|-+-+-Q1     | |
+-|-|K  |            | |
| +-|>  |   +--------+ |
| | +---+   |          |
+-|-------+ |          |
| +---+ | |          |
+--|-|J Q|-+-+-Q0       |
+--|-|K  |              |
|  +-|>  |              |
|  | +---+              |
+-----------------------+
|                    |
clk                  ENT
```
Here, we are counting a 4-bit binary code for as long as the "enable toggle" (ENT) input is asserted. The Q output of the previous stage determines whether or not the JK Flip-Flop in the next state will toggle or not, with one toggle per clock pulse. The output number appears on Q3-Q0.

This device is also a ring counter, as it will reset its count back to 0000 after counting 1111, forming an infinite loop.

Upon reaching 1111, the AND causes "terminal count" (TC) to be asserted if ENT is also asserted. By connecting this TC to the ENT on another ripple counter we can extend this scheme beyond 4 bits--the next ripple counter simply becomes bits 4-7.