sigma-delta ADC

Sigma-delta analog to digital converters (or noise-shaping ADCs) are devices that rely on massive oversampling (or supersampling) instead of small quantization step to represent precisely an input analog signal as a series of bits. It is thus possible to build ADCs using only a single comparator, at the condition of sampling at a much higher rate than the Nyquist frequency.

The structure of a typical sigma-delta ADC is presented below:

                        Q
                        |
         +     |---|    |+
    X ----O----|1/s|----O---|--> Y
          |-   |---|   +    |
          |                 |
          |-----------------|

where X represents the input analog signal, the 1/s block is an integrator (see Laplace transform) having a frequency response which is proportional to 1/f, Q represents the quantization noise added by the comparator (which is nothing else than a 1-bit ADC), and Y is the output signal to be sampled. The name of this structure comes from the fact that the signal is "summed" (sigma) by the integrator, and the output is subtracted (delta) from the input to form a negative feedback loop. It can be shown that Q is a non-correlated white noise, that is, with a spectrum that is constant on all frequencies.

If we write Y as a function of X and Q, and assuming the frequency response of the integrator to be simply 1/f in modulus, we see that

(X-Y)/f + Q = Y

f(Y-Q) + Y = X

Y = (X+fQ)/(f+1)

which means that the output Y is composed of a low-pass filtered version of X, X/(f+1), and a high-pass filtered version of Q, fQ/(f+1). The cut-off frequency for both filters is the same, so that at the output, the signal and the quantization noise are separated spectrally. Remember that the output dynamic range is only 1 bit, and the signal is repeatedly HI and LO, never in between. However, applying a numerical low-pass filter on this series of zeros and ones eliminates most of the quantization noise, and a high dynamic range numerical representation of the analog signal is produced, using only one comparator to do the job.

The downside of sigma-delta ADCs is that the sampling rate must be extremely high since only a small portion of the bandwidth at the output contains the useful signal. There is many variants of this structure, including multiple-stage sigma-delta ADCs and higher-order sigma-delta ADCs; one can also use a conventional ADC instead of a single comparator to boost the dynamic range if the high sampling rate is not a problem. The integrator can be replaced by a R-C circuit for a cheaper, less efficient ADC.