IEEE standard 1076.
VHDL stands for "VHSIC Hardware Description Language".
VHDL (and other hardware description languages) are used to describe digital circuits. The idea is to provide a way to describe circuits, so useful things (like processors) can be built up from transitors. With transistor counts for modern CPUs in the 50 million range (for a Pentium 4), this is a decidedly non-trivial ask.
VHDL is a serious HDL, the one that's generally used for serious processor design. The big-name implementation is by Synopsys (which also implements Verilog). Synopsys claims to be used by ARM, IBM, NVIDIA and Sun. It is also often used by Universities and research labs.
Descriptions of circuits in VHDL are typically hierarchial. The designer creates components, called entities. The entities are roughly equivalent to function prototypes in C. They describe the component, giving its name and input and output connections, called ports. So, you might start by creating an entity for a chip's datapath and then further specifying that in terms of registers, adders, etc.
To specify the behaviour of a entity, is described by an architecture. An architecture is a particular implementation of the desired behaviour. These can be behavioural descriptions, which indicate that a part should behave this way or they can be structural, which indicate how the entity is put together from smaller entities which are wired together. You can have multiple architectures for a single entity. This allows you to test different implementations of the same component.
Behavioural descriptions are given with a description language that looks a lot like a programming language. The designer can use this language to calculate what the output should be, based on the inputs. Timing can also be specified, so you would indicate that when the input changes, the output will change after a time delay, to represent the propagation delay of the circuit.
When a circuit is described, the next step is usually simulation. VHDL simulators take a circuit description and simulate what would happen if it was actually implemented. Usually, the circuit is connected (virtually) to a testbench which simulates input signals. In the simulator, the designer can check to make sure the output signals and timing meet expectations.
Once a circuit has been fully designed and debugged, it can be synthesized. Synthesis is the process of taking a VHDL model to a real chip. The target is typically an ASIC or FPGA, depending on use, requirements and volume. Not all VHDL architecture descriptions can be synthesized. The behavioural description language is too complicated to translate arbirtary expressions to silicon. Different implementations can handle different code and the designer must keep this in mind when doing the final designs.