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This is the time that an incoming signal takes to propagate from the input to the output of a logic gate. It´s a main factor of the speed of devices, such as the CPU of your computer. The reason for this delay usually lies, like almost always in electrical engineering, in the time it takes to charge/discharge a capacitor. Consider the following CMOS inverter:
         VDD
          |
          |
        |-
     +--|
     |  |-
     |    |
A ---+    +---- B
     |    |
     |  |-
     +--|
        |-
          |
          |
         VSS
To propagate a change in the input A to the output B your have to open one transistor and to close the other one. This means that the gate capacitors have to be charged/discharged. There are also other, so-called parasitic capacitances, like from interconnects, that have to be considered. Due to the minuscule size of today´s logic structures this process won´t take long, but cannot be neglected.

Thís charge/discharge mechanism is also the main reason why a logic circuit needs power to operate.

What design decisions influence the propagation delay ?

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