Rendezvous circuits are used in asynchronous system designs to control when a certain action can be started based on whether two or more previous actions have been completed successfully.
A GasP circuit is a new kind of rendezvous circuit that evolved from an earlier family of circuits designed by Charles E. Molnar, at Sun Microsystems. This previous circuit was named asP*, as in asynchronous symmetric pulse protocol. Sun's Asynchronous Design Group added the G in front of its incarnation, because "GasP is what you are supposed to do when you see how fast our new circuits go."1
As an example, GasP circuits can be used to control the data flow in an asynchronous data pipeline. The pipeline is made up of a number of sections divided by data latches. These latches are controlled by GasP circuits and only open when the data is available at the input side, and the section downstream is empty and ready to receive the new data.
Each GasP circuit has connections to its neighbours (one upstream and one downstream) and one connection to the data latch it controls. When it receives a signal from its upstream neighbour that data is available on the pipeline and from its downstream neighbour that the section downstream is empty, its internal logic opens up the latch to enable the data to pass on to the next section. This signal is also used to turn the incoming signal back to normal, thereby signaling to its neighbour upstream that the section is empty again, and in the same stroke causes the latch to close up again. The same signal is also used to tell the neighbour downstream that there is data on its incoming section and thus the neighbour downstream runs through the whole procedure in turn.
The internal logic of a GasP circuit is made up of a NAND gate (which produces a FALSE signal if, and only if, both its inputs are TRUE), a number of inverters (three actually), a pull-up transistor and a pull-down transistor. The general layout is something like this:
---
|
|
pull-up
transistor ---\
| |
| |
| \ downstream
>--------------------- inverter -----\ /------------------------>
upstream / | | |
| | | |
| NAND |
| gate |
| | |
| | |
\-------------------|--- inverter --- pull-down
| transistor
| |
inverter |
| ---
| -
|
data pipeline data
>=================================== latch =======================================>
In its initial state (both data sections empty) the incoming and outgoing connections are TRUE, while the signal to the data latch is FALSE. From there you should be able to figure out what happens when data arrives on the pipeline and the upstream neighbour tells the GasP circuit it has data on the pipeline (incoming signal becomes FALSE).
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1 Quote from Scientific American, August 2002 issue. Article starting on page 46: Computers without clocks, by Ivan E. Sutherland and Jo Ebergen. Quote from page 51, left column, third paragraph.
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Sources:
Scientific American; August 2002 issue, page 46: Computers without clocks by Ivan E. Sutherland and Jo Ebergen.
http://www.sciam.com/ - search for GasP.